This course introduces the system-on-chip (SoC) implementation flow through AI-driven EDA design methodologies, with a focus on physical implementation challenges at advanced FinFET technology. Key topics include placement, routing, and the optimization of performance, power, and area (PPA), helping participants develop practical expertise in advanced-process SoC implementation.
This course aims to provide participants with a comprehensive understanding of the integration of FinFET physical design workflows with EDA AI technologies. The program emphasizes concurrent optimization of Performance, Power, and Area (PPA) to address the increasing complexity of advanced‑node SoC designs. Through a strong hands‑on approach, participants will gain practical experience using EDA AI accelerators and learn best practices for high‑performance SoC physical design, enabling them to apply AI‑driven methodologies effectively in real‑world design scenarios.
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