SiCADA 600 SoC Design and Function Verification with GenAI

This course trains engineers in both Digital Design (DD) and Design Verification (DV) using GenAI as a collaborative engineering partner. Students progressively design and verify four RTL modules — Register Block, RX Engine, Async FIFO, and DMA Controller — and ultimately integrate them into a complete RX Receiver with AHB DMA Controller SoC. Every student practices both DD and DV during the first six weeks, ensuring cross-functional understanding before splitting into specialized roles for the Final Project. Beyond RTL design, the course integrates SVV and UVM methodologies, with Verdi as the primary debug platform throughout. GenAI serves three roles: IC Engineering Assistant, Self-learning Assistant, and AI-assisted Reflection partner. The GenAI Prompt Guide — capturing prompts, design decisions, and engineering insights — serves as a technical portfolio artifact that directly supports behavioral interviews. The course develops four core capabilities that define industry-ready engineers: Spec Comprehension & Analysis, System-Level Thinking, RTL Design & Verification Proficiency, and Debug Proficiency in the GenAI era.

Upon completing this course, students will be able to: (1) Front-End Technical Mastery — Deliver synthesizable RTL and complete UVM testbenches covering the full front-end flow, from spec to simulation closure; (2) Verification Platform Development — Build a full UVM verification environment with multi-agent architecture, scoreboard, reference model, and functional coverage; (3) GenAI Engineering Proficiency — Apply GenAI effectively as an IC Engineering Assistant, Self-learning Assistant, and AI-assisted Reflection partner across all assignments; (4) SoC Integration Awareness — Reason about cross-module integration, AHB/APB bus protocols, CDC handling, and system-level debug under realistic bus contention conditions; (5) Engineering Portfolio — Produce a GenAI Prompt Guide demonstrating traceable engineering judgment, serving as a concrete portfolio deliverable for industry hiring.