SiCADA 500 Universal Verification Methodology

[2026在職人士專班] This UVM (Universal Verification Methodology) course is designed to help students build a solid understanding of modern verification methodology and develop hands-on skills in constructing a complete UVM environment. The course begins with fundamental concepts and introduces key UVM components, including: • uvm_object and uvm_component and their respective roles • uvm_report_object for message reporting and debugging • uvm_phase for testbench execution control • uvm_config_db for configuration management • TLM (Transaction-Level Modeling) for inter-component communication • sequence, driver, monitor, and scoreboard for data flow and checking • and coverage for measuring verification completeness The course adopts a “theory + guided lab” approach. Through a series of structured exercises, students will be guided step-by-step to implement a full UVM testbench — from building the environment and connecting components, to driving transactions, collecting functional coverage, and analyzing verification results. This hands-on approach bridges theory and practice effectively. In addition, two homework assignments are provided to reinforce learning. Each focuses on applying UVM concepts to different design examples, allowing students to practice adapting UVM components to various verification scenarios. Overall, this course balances theoretical depth with practical application, making it ideal for engineers and graduate students who wish to strengthen their foundation and confidently develop UVM-based verification environments.

By the end of the course, students will be able to: • Understand the structure and purpose of key UVM components, including object, component, phase, config_db, and TLM communication. • Construct a complete UVM testbench incorporating sequences, drivers, monitors, scoreboards, and coverage. • Apply UVM configuration and reporting mechanisms for flexible and reusable verification environments. • Analyze and improve verification quality using functional coverage and reporting. • Integrate theoretical knowledge through guided labs and independent homework to handle different design verification scenarios confidently.