Advanced Design Verification

[2025在學學生專班] This course teaches worldwide leading-edge verification methodologies, including formal and functional verification, which work together to significantly reduce verification time. Functional verification includes setting up a testbench using UVM and SystemVerilog. Formal verification course uses Synopsys' VC Formal to quickly find potential design defects that are not easily found by functional verification in an algorithmic way. In this class, you will explore verification planning, testbench architecture, and how to leverage functional coverage metrics to exhaustively test digital designs to ensure zero-defect IC development. In addition to the verification capability, this course also includes two design units from “Verilog Design Methodology” course: “IC Design Foundations” and “Practical Verilog Design”. These arrangement will give you the basic literacy in Verilog digital design and allow you to build a full set of capabilities to perform the work of a verification engineer well.

After completing this course, you will be familiar with various formal verification methods such as connectivity checking (CC) and sequential equivalence checking (SEQ) to ensure the correctness of the design. You will also learn the world's most advanced verification methodology UVM in the field of function verification. Through the lab and homework exercises, you can not only further develop your ability to write test benches by using SystemVerilog and UVM, but also begin to build a UVM test environment to independently test your designs. In addition, the two design courses from VDM also provide corresponding assignments for you to practice basic Verilog design skills, to make you own comprehensive IC verification capabilities to easily connect with IC industry world.