SiCADA 500 SoC Backend Implementation

[2025在學學生專班] Delve into the critical phase of SoC design that takes the synthesized frontend data into a physical form. This course covers everything from block floor planning and power planning to routing and post-layout verification. Understand the nuances of clock tree synthesis, and signal integrity. Get hands-on experience with the latest EDA tools to ensure your designs meet the stringent specifications of performance, power, and area.

After completing this course, you will be familiar with automatic place-and-route technology to effectively improve design efficiency and quality. You can also master the key concepts of STA and UPF to ensure that the design meets timing and power consumption requirements。