The goal of this course is to lower the barrier for one to transform what learned HDL language knowledge into hand-on design skill expected from IC industry. This rich-content course uses lots of practical examples to make you quickly familiar with the best practice Verilog design skills and own the capability to be fully qualified engineers in many fields. This course is a perfect fit for one who is targeting to be a digital designer or digital verification engineer, also nice for one is eager to be a frontend engineer.
Starting from how to take care of your working environment to increase personal productivity, followed by guiding you to construct your own design and testbench step by step, for example how to design a FSM, by using Verilog is the main benefit you can get from this course. This offers you the opportunity to transform your Verilog knowledge to solid design skill quickly. In addition to design itself, basic verification skill and coding style is also offered by this course, to increase your design quality and readability as you will be expected from the industry in the future. You can easily familiarize yourself with industry-standard design methodologies, tools, and begin designing digital components at course end.
請先報名課程,報名完成後即可參與討論
討論區僅於授課期間開放
凡報名任一SiCADA IC 學院的課程,皆須填寫報名問卷供管理員審核資格,請填寫下方問卷以利後續報名流程。以下資訊已自動帶入會員資料,如編輯會自動幫您更新會員個資。
※供客服聯繫,請務必確實填寫
※需填寫同護照姓名
※顯示於證書,請務必確實填寫
※供客服聯繫,請務必確實填寫
※供客服聯繫,請務必確實填寫
(上傳檔案以1個為限,內容須包含在職證明、工作證或在學證明、學生證正反面。應屆畢業生請提供畢業證書以茲證明)
※送出後無法修改,可在會員專區的訂單查詢頁檢視內容
※如有驗證問題,請與管理員聯絡
Training&Evaluation 同意書內容已更新,請點擊下方「Training&Evaluation 同意書」開啟視窗閱讀更新內容,且勾選下方同意書,確認送出後,才可繼續觀看課程影片。