500 課程

SiCADA 500 Program

Verilog Design Methodology

Course Introduction
The goal of this course is to lower the barrier for one to transform what learned HDL language knowledge into hand-on design skill expected from IC industry. This rich-content course uses lots of industry practical examples, different forms of homework exercises and intensive homework Q&A to make you quickly familiar with the best practice Verilog design skills and own the capabilities to be fully qualified engineers in many fields. This course is a perfect fit for one who is targeting to be a digital designer or digital verification engineer, also nice for one who is eager to be a frontend engineer.

Course Objectives
Starting from how to take care of your working environment to increase personal productivity, followed by guiding you to construct your own design and testbench step by step, for example how to use FSM for control and data path design, how to handle asynchronous design properly…etc by using Verilog is the main benefit you can get from this course. Through various industry level homework practices, this course offers you the opportunity to strengthen your design skill quickly and transform your Verilog design much closer to what industry expected from a qualified engineer. In addition to design itself, industry design best practices, useful design tips and coding style are also offered by this course, to increase your design quality and readability as you will be expected from the industry in the future. You can easily familiarize yourself with industry-standard design methodologies, tools, and begin designing digital components at course end.

Target Audiences
One who targets to be a digital designer, digital function verification engineer or SoC front-end engineer.

Prerequisites
To enroll in the Verilog Design Methodology, students are assumed to

  • Have a solid understanding of Digital Designs, Digital Circuits or Digital Systems, especially combinational and sequential designs
  • Be familiar with Verilog Hardware Description Language
  • Be familiar with Unix/Linux environment and relative Editors in Unix environment
  • RTL Coding experience is not must but a plus

Advanced Design Verification

Course Introduction
This course teaches worldwide leading-edge verification methodologies, including formal and functional verification, which work together to significantly reduce verification time. Functional verification includes setting up a testbench using UVM and SystemVerilog. Formal verification course uses Synopsys' VC Formal to quickly find potential design defects that are not easily found by functional verification in an algorithmic way. In this class, you will explore verification planning, testbench architecture, and how to leverage functional coverage metrics to exhaustively test digital designs to ensure zero-defect IC development. In addition to the verification capability, this course also includes two design units from “Verilog Design Methodology” course: “IC Design Foundations” and “Practical Verilog Design”. This arrangement will give you the basic literacy in Verilog digital design and allow you to build a full set of capabilities to perform the work of a verification engineer well.

Course Objectives
After completing this course, you will be familiar with various formal verification methods such as connectivity checking (CC) and sequential equivalence checking (SEQ) to ensure the correctness of the design. You will also learn the world's most advanced verification methodology UVM in the field of function verification. Through the lab and homework exercises, you can not only further develop your ability to write test benches by using SystemVerilog and UVM but also begin to build a UVM test environment to independently test your designs. In addition, the two design courses from VDM also provide corresponding assignments for you to practice basic Verilog design skills, to make you own comprehensive IC verification capabilities to easily connect with IC industry world.

Target Audiences
One who targets to be digital design verification engineer.

Prerequisites
To enroll in the Advanced Design Verification course, students should

  • Be good at Object Oriented Programming (OOP) Language like C++ or Python and relative S/W debugging skills
  • Be familiar with Digital Designs, Digital Circuits or Digital Systems
  • Be familiar with HDL languages like Verilog or VHDL
  • Be familiar with Unix shell and scripting
  • Have basic knowledge of SystemVerilog is a plus

Universal Verification Methodology

Course Introduction
This course teaches worldwide leading-edge function verification methodology – Universal Verification Methodology. Functional verification includes setting up a testbench by using UVM and SystemVerilog. In this class, you will explore verification planning, testbench architecture, and how to leverage functional coverage metrics to exhaustively test digital designs to ensure zero-defect IC development.

Course Objectives
After completing this course, you will learn the world's most advanced verification methodology UVM in the field of function verification. Through the lab and homework exercises, you can not only develop your ability to write testbench by using SystemVerilog and UVM but also begin to build a UVM test environment to independently test your designs. 

Target Audiences
One who targets to be a design verification (DV) engineer or a digital designer (DD).

Prerequisites
To enroll in the Universal Verification Methodology course, students should

  • Be good at Object Oriented Programming (OOP) Language like C++ or Python and relative S/W debugging skills
  • Have basic understanding of SystemVerilog, especially in OOP, interfaces, randomization and constraints, transactions, IPC and functional coverage (covergroup and coverpoint) relative fields
  • Be familiar with Digital Designs, Digital Circuits or Digital Systems
  • Be familiar with HDL languages like Verilog or VHDL
  • Be familiar with Unix shell and scripting

SoC Frontend Implementation

Course Introduction
This comprehensive course is designed to help you quickly gain expertise as a front-end digital design engineer by providing both in-depth knowledge and practical skills in key areas , including: 

  • Logic synthesis
  • Timing constraints and static timing analysis
  • Formal verification
  • Low-power design using Unified Power Format (UPF) 

You will explore best practices for synthesis using 

  • Synopsys Design Compiler – industry-leading synthesis tool
  • Formality – for formal verification
  • PrimeTime – for timing analysis
  • VCS-NLP – for simulation and verification 

Through lectures and guided lab sessions, you will learn to synthesize digital circuits, verify functional integrity, analyze timing, and implement power-efficient designs. This course is tailored to equip you with the technical skills and industry knowledge necessary to achieve your design goals and seamlessly connect with the IC industry environment. 

Course Objectives
The objective The objective of this course is to equip participants with the practical expertise needed to design, verify, and optimize digital systems at the RTL level, preparing them to tackle the complexities of real-world SoC projects using industry-leading Synopsys tools. 
The course focuses on four essential front-end digital design methodologies: 

  • Synthesis: Generate netlists optimized for Performance, Power, and Area (PPA)
  • Static Timing Analysis (STA): Ensure design specifications are accurately captured and verified
  • Low Power Design (UPF): Specify power goals and build effective power-saving structures using Unified Power Format
  • Formal Verification: Confirm functional correctness and alignment between the netlist and original RTL

By the end of the course, participants will be able to effectively apply industry-standard workflows and best practices to optimize, verify, and analyze digital circuits for performance, functional integrity, and power efficiency. 

Target Audiences
One who targets to be a digital design engineer or design and verification engineer.

Prerequisite
To enroll in the SoC Frontend Implementation course, students should be familiar with 

  • Have a basic understanding of RTL (Register Transfer Level), Digital Designs, Digital Circuits or Digital Systems, especially combinational and sequential designs
  • Be familiar with chip vs. block hierarchy, clock tree vs. data path, STA, pre-layout and post-layout correlation is beneficial
  • Have prior experience and knowledge with EDA synthesis tools is not must but a plus
  • Be familiar with Unix environment, relative editors, and Tcl commands 

SoC Backend Implementation

Course Introduction
This course focuses on the critical phase of System-on-Chip (SoC) design, transitioning synthesized frontend data into physical design implementation for chip manufacturing. You will gain a comprehensive understanding of the entire physical design flow, including:

  • Design Setup
  • Top-Level and Block-Level Floorplanning
  • Power Planning
  • Cell Placement
  • Clock Tree Synthesis (CTS)
  • Routing
  • Post-Layout Verification 

Through hands-on exercises, you will tackle real-world challenges such as timing closure and congestion debugging, building practical experience in physical design. The course also covers advanced topics like clock tree synthesis nuances and signal integrity considerations. 
By working with the latest EDA tools, you will learn how to meet stringent performance, power, and area (PPA) requirements, ensuring your designs are optimized for modern semiconductor standards.

Course Objectives
By the end of this course, you will:

  • Gain a comprehensive understanding of the chip physical design flow—from initial design input to final sign-off for tape-out and chip manufacturing
  • Develop the ability to collaborate effectively with the frontend design team to achieve PPA (Power, Performance, Area) closure
  • Learn to identify and resolve timing and routing congestion challenges, acquiring critical skills for design closure and debugging
  • Master automatic place-and-route technologies to enhance design efficiency and quality
  • Understand key concepts of Static Timing Analysis (STA) and Unified Power Format (UPF) to ensure designs meet timing and power consumption targets 

Target Audiences
One who targets to be a full-chip physical design integration engineer or physical design engineer. 

Prerequisite
To enroll in the SoC Backend Implementation course, students are assumed to 

  • Have a solid understanding of Digital Designs, Digital Circuits or Digital Systems, especially combinational and sequential designs
  • Be familiar with basic concepts of floor planning, standard cell and macro usage, placement and routing fundamentals, STA, and the causes and effects of congestion
  • Have prior experience and knowledge with EDA APR tool knowledge is not must but a plus
  • Be familiar with Unix and Tcl commands 

Analog Circuit Design

Course Introduction
This course is taught by experts with over 30 years of teaching and industry experience, guiding students step-by-step into the field of analog circuit design. It covers the fundamental principles of CMOS amplifier design and provides hands-on training using world-leading EDA tools for simulation and analysis. With instruction from experienced application engineers, students will quickly become proficient in tool usage and design workflows. The course also explores the mindset and considerations behind mixed-signal design, sharing practical design tricks and checklists commonly used in the industry to help learners build the methodology and thinking needed to become analog design experts.

Course Objectives
The course’s target is to teach the basic knowledge of analog circuit design through hands-on exercises with practical tools. By learning from IC industry experts to quickly grasp design concepts and avoid wasting too much time on failures.

Target Audiences
One who are targeting to be a mixed signal / Analog IC designer, sensor Analog IC design expert or Analog system designer / leader.

Prerequisite
To enroll in the Analog Circuit Design course, students are assumed to

  • Have a foundational understanding of analog circuit principles, especially in CMOS technology
  • Be familiar with amplifier structures, DC bias points, small-signal models, and frequency response evaluation
  • Be comfortable using simulation tools
  • Have a basic grasp of analog IC design concepts
  • Have prior experience with practical design considerations is beneficial