500 課程
Verilog Design Methodology
Course Introduction
The goal of this course is to lower the barrier for one to transform what learned HDL language knowledge into hand-on design skill expected from IC industry. This rich-content course uses lots of industry practical examples, different forms of homework exercises and intensive homework Q&A to make you quickly familiar with the best practice Verilog design skills and own the capabilities to be fully qualified engineers in many fields. This course is a perfect fit for one who is targeting to be a digital designer or digital verification engineer, also nice for one who is eager to be a frontend engineer.
Course Objectives
Starting from how to take care of your working environment to increase personal productivity, followed by guiding you to construct your own design and testbench step by step, for example how to use FSM for control and data path design, how to handle asynchronous design properly…etc by using Verilog is the main benefit you can get from this course. Through various industry level homework practices, this course offers you the opportunity to strengthen your design skill quickly and transform your Verilog design much closer to what industry expected from a qualified engineer. In addition to design itself, industry design best practices, useful design tips and coding style are also offered by this course, to increase your design quality and readability as you will be expected from the industry in the future. You can easily familiarize yourself with industry-standard design methodologies, tools, and begin designing digital components at course end.
Target Audiences
One who targets to be a digital designer, digital function verification engineer or SoC front-end engineer.
Advanced Design Verification
Course Introduction
This course teaches worldwide leading-edge verification methodologies, including formal and functional verification, which work together to significantly reduce verification time. Functional verification includes setting up a testbench using UVM and SystemVerilog. Formal verification course uses Synopsys' VC Formal to quickly find potential design defects that are not easily found by functional verification in an algorithmic way. In this class, you will explore verification planning, testbench architecture, and how to leverage functional coverage metrics to exhaustively test digital designs to ensure zero-defect IC development. In addition to the verification capability, this course also includes two design units from “Verilog Design Methodology” course: “IC Design Foundations” and “Practical Verilog Design”. This arrangement will give you the basic literacy in Verilog digital design and allow you to build a full set of capabilities to perform the work of a verification engineer well.
Course Objectives
After completing this course, you will be familiar with various formal verification methods such as connectivity checking (CC) and sequential equivalence checking (SEQ) to ensure the correctness of the design. You will also learn the world's most advanced verification methodology UVM in the field of function verification. Through the lab and homework exercises, you can not only further develop your ability to write test benches by using SystemVerilog and UVM but also begin to build a UVM test environment to independently test your designs. In addition, the two design courses from VDM also provide corresponding assignments for you to practice basic Verilog design skills, to make you own comprehensive IC verification capabilities to easily connect with IC industry world.
Target Audiences
One who targets to be digital design verification engineer.
SoC Frontend Implementation
Course Introduction
This comprehensive course is designed to help you quickly gain expertise as a front-end digital design engineer by providing both in-depth knowledge and practical skills in key areas, including logic synthesis, timing constraints and static timing analysis, formal verification, and low power design using Unified Power Format (UPF). You will explore best practices for synthesis using Synopsys Design Compiler, the world’s leading synthesizer tool, and gain hands-on experience with other industry-standard Synopsys tools such as Formality, PrimeTime, and VCS-NLP. Through lectures and guided lab sessions, you will learn to synthesize digital circuits, verify functional integrity, analyze timing, and implement power-efficient designs. This course is tailored to equip you with the technical skills and industry knowledge necessary to achieve your design goals and seamlessly connect with the IC industry environment.
Course Objectives
The objective of this course is to equip participants with the practical expertise needed to design, verify, and optimize digital systems at the RTL level, preparing them to tackle the complexities of real-world SoC projects. Using industry-leading Synopsys tools, the course focuses on four essential front-end digital design methodologies: synthesis for delivering netlists optimized for Performance, Power, and Area (PPA); static timing analysis (STA) to ensure that design specifications are accurately captured and verified; low power design with Unified Power Format (UPF) to specify power goals and construct effective power-saving structures; and formal verification to ensure functional correctness and alignment between the netlist and the original RTL. By the end of the course, participants will be able to effectively apply industry-standard workflows and best practices to optimize, verify, and analyze digital circuits for performance, functional integrity, and power efficiency.
Target Audiences
One who targets to be a digital design engineer or design and verification engineer.
SoC Backend Implementation
Course Introduction
Delve into the critical phase of SoC design that takes the synthesized frontend data through physical design implementation for chip manufacturing. This course covers the whole physical design flow from design setup, top and block level floor planning and power planning, cell placement, clock tree synthesis, routing and post-layout verification. Hands-on challenges and debugging on timing and congestion to gain real-life design experience. Also understand the nuances of clock tree synthesis, and signal integrity. Get hands-on experience with the latest EDA tools to ensure your designs meet the stringent specifications of performance, power, and area (PPA).
Course Objectives
After completing this course, you will be familiar with the chip physical design flow from design input all the way to final sign-off for tape out to chip manufacturing. You will also gain the ability to communicate efficiently with frontend design team for design PPA closure. You will be exposed to design timing and routing congestion challenges and gain the critical design closure skills to debug the issues and to find solutions for design closure. You will learn the automatic place-and-route technology to effectively improve design efficiency and quality. You can also master the key concepts of STA and UPF to ensure that the design meets timing and power consumption targets.
Target Audiences
One who targets to be a full chip physical design integration engineer or physical design engineer.
Analog Circuit Design
Course Introduction
This course is taught by experts with over 30 years of teaching and industry experience, guiding students step-by-step into the field of analog circuit design. It covers the fundamental principles of CMOS amplifier design and provides hands-on training using world-leading EDA tools for simulation and analysis. With instruction from experienced application engineers, students will quickly become proficient in tool usage and design workflows. The course also explores the mindset and considerations behind mixed-signal design, sharing practical design tricks and checklists commonly used in the industry to help learners build the methodology and thinking needed to become analog design experts.
Course Objectives
The course’s target is to teach the basic knowledge of analog circuit design through hands-on exercises with practical tools. By learning from IC industry experts to quickly grasp design concepts and avoid wasting too much time on failures.
Target Audiences
One who are targeting to be a mixed signal / Analog IC designer, sensor Analog IC design expert or Analog system designer / leader.